In the context of the present invention, a logic unit designates a digital functional block which may receive data and/or send data. The data may include instructions. Logic units may be dedicated to a specific data processing operation or programmable to perform a class of data processing operations. Generally, logic units are characterized to generate data (only send), to consume data (only receive), or to transform data (send and receive). Examples for data processing operations are multimedia signal processing, communication protocol processing, and system maintenance and monitoring operations.
Logic units can be realized as software applications running on a computer. Logic units realized as software applications are described in a programming language, for example in C or C++. Logic units can also be realized inside a Field Programmable Gate Array (FPGA). Logic units realized in an FPGA are described in a Hardware Description Language (HDL), for example in the languages VHDL or Verilog and will be called HDL design entities or HDL entities in the present specification. Logic units may also be realized in integrated circuits. Logic units realized or to be realized in integrated circuits may be simulated by logic units realized in an FPGA. An FPGA may comprise a plurality of logic units.
An FPGA system comprises multiple Field Programmable Gate Arrays and an infrastructure that allows users to utilize the FPGAs. In an FPGA system a logic unit may also be distributed on several FPGAs. The FPGAs are configured by transmitting the HDL description onto the FPGAs. The structure of the circuitry inside the FPGA is thus defined and a dedicated logic circuit comprising a logic unit or logic units is configured. An FPGA system may be used either as Rapid Prototyping Platform or as a so called supercomputer.
For Rapid Prototyping, a digital system developer writes a HDL description of an intended digital processing system to be manufactured as an integrated circuit, for example a Si-chip (Si —silicon). An FPGA system may be used to map or emulate the behavior of the chip, i.e. the HDL description is loaded onto the FPGA system. Additionally, if the digital processing system contains programmable logic, the FPGA system allows software engineers to start working before the actual chip is available. They may program on the FPGA system. This allows the digital system developer to debug the HDL using full-size applications, where all elements of the final Si-chip and the required application software running on programmable data processing unit inside the Si-chip are running.
The HDL design may be processed by Electronic Design Automation (EDA) tools. Although different EDA tools are needed to generate chip production files and FPGA configuration files, the HDL description is the same (except for some technology-specific parts). Errors in the HDL description can therefore be already detected in the FPGA system, i.e. prior to tape-out of the silicon production files, thus reducing both cost and development time.
For supercomputing, the HDL description utilizes the highly parallel and regular nature of the FPGA architecture for the acceleration of equally parallel and regular computations.
One of the key features provided by any FPGA system's infrastructure is a communication access. Communication is required for example for transferring the FPGA configuration bit stream from a remote location, for debugging the HDL design inside the FPGAs, and for collaboration between software running on a remote machine and HDL designs running inside the FPGAs. Modern FPGA systems may be connected to a Host PC through a device access unit (DAU).
Communication is further needed for data transfer between logic units. Difficulties for the communication may arise from the different kinds of logic units, realized as software applications and/or as HDL entities. Communication may further be hindered by different processing speed of different logic units and by a different size of data units required by different logic units.